Line driver

ABSTRACT

The invention relates to a line driver arrangement for driving signals via at least one subscriber line, provided with:  
     an input for injecting an input signal and having an output at which a signal which is to be driven via the subscriber line can be tapped off,  
     a digital amplifier which produces a pulse-width-modulated signal on the output side from the input signal or from a signal derived from it,  
     an analog amplifier, which produces an analog signal on the output side from the input signal or from a signal derived from it,  
     with the outputs of the amplifiers being coupled such that the signal to be driven results from superimposition of the analog signal and the digital signal,  
     with the gain of the analog amplifier being matched to the gain of the digital amplifier such that scatter and/or overshoot on the digital signal are at least reduced after the superimposition.

[0001] The invention relates to a line driver arrangement for drivingsignals via at least one subscriber line.

[0002] High bit rate data transmission on a subscriber line is of verymajor importance in modern telecommunications, where there is a need totransmit both speech and data signals via the respective subscriberlines in the telephone network.

[0003] This is achieved by means of so-called xDSL technology, where DSLis short for “digital subscriber line”. With this technique, thetelecommunications line, which is typically composed of copper, issubdivided into at least two different channels. As before, one of thesechannels is available for the conventional telephone services, that isto say for speech transmission (POTS, plain old telephone service). Atleast one second channel is used for data transmission.

[0004] One known representative of xDSL technology is the so-called ADSLtechnique (“asymmetric digital subscriber line”), which refers to atechnique which allows a high bit rate bit stream to be transmitted froma control center to the subscriber, and allows a low rate bit streamfrom the subscriber to the control center. Since this transmissiontechnique uses an asymmetrical bit rate, an ADSL system is particularlyhighly suitable for services such as video on demand, or else forInternet applications.

[0005] The ADSL method is a digital transmission method for typicallytwisted two-wire lines in the telephone network to the end subscriberfor broadband applications. A digital signal processor (DSP) is providedfor each channel, and is operated using a relatively low supply voltageof, for example, +5 V. In order to allow the signals to be transmittedat an adequate signal strength via the subscriber lines, each of thesignal processors is followed by line driver circuits. A line drivercircuit such as this is, in the simplest case, an amplifier whichtransmits the signal to be transmitted on the subscriber line with thenecessary gain, since losses in the signal to be transmitted always haveto be taken into account as well, during signal transmission.

[0006] These line driver circuits are subject to very stringentlinearity and signal bandwidth requirements, particularly in the channelfor data signal transmission, but also in the speech signal channel.

[0007] A further problem results from the fact that the amplification ofthe signal very frequently results in the signal to be transmitted beingdistorted.

[0008] There are already a large number of different circuit variantsfor providing a line driver circuit, some of which will be describedbriefly in the following text:

[0009] A Class AB amplifier is described in the article by Michael S.Kappes, “A 3-V CMOS Low-Distortion Class AB Line Driver Suitable forHDSL Applications”, IEEE JSSC, Vol. 35, No. 3, March 2000. An amplifiersuch as this has a relatively low efficiency of about 15% when used forADSL, which leads to an increased power consumption in the range from800 mW to 1 W. In order to now achieve the required gain linearity, thisamplifier has to use a current which is as small as possible, althoughthis would mean that the capability to reduce the supply voltage betweenthe line driver and the downstream transformer is restricted. This isassociated with an increase in the electrostatic charge (ESD), resultingin problems from overheating of the transformer. There may also beproblems involved with technology transfer.

[0010] Furthermore, Class G amplifiers are also known, and their designand method of operation are described, for example, in the article by J.Pierdomenico, et al. “A 744 mW Supply Full-Rate ADSL CO Driver”, ISSCC20/2, Session 19, pages 320 et seq, 2002. The efficiency of a Class Gamplifier such as this is better than that of a Class AB amplifier, andthis also leads to a reduced power consumption. This is because, in thecase of signals with a high crest factor (Peak-to-Average Ratio=PAR),the mean output voltage is very much lower than the maximum of theoutput voltage. However, this is offset by very severe distortion of thetransmitted signal, owing to the very frequent supply voltage switchingprocesses that occur with this amplifier class. Furthermore, thisamplifier class is very much less efficient, particularly when thetransmitted signals have a low crest factor. Since, however, futuresystems will operate with reduced crest factors, this problem willbecome increasingly important in the near future.

[0011] Furthermore, Class D amplifiers also exist, which operate as PWMmodulator circuits (Pulse Width Modulator). One representative of thisamplifier class is, for example, described in the article by Jae H.Jeong et. al. “A Class D Switching Power Amplifier with High Efficiencyand Wide Bandwidth by Dual Feedback Loops”, IEEE InternationalConference on Consumer Electronics (ICE '95), pages 428 et seq, 1995.Class D amplifiers admittedly have a very high efficiency in the rangefrom 80 to 90%, but this is at the expense of very wide scatter.

[0012] In order to reduce the scatter, and hence to improve thelinearity, feedback circuits are known, but these generally lead to thestability of the overall circuit being relatively poor. One such circuitwith feedback is described, for example, in the Korean PatentApplication No. 96/37905. A further problem associated with Class Damplifiers results from their very high switching speed. In particular,the switching speed is very much higher than the changes in themathematical signs in the signal to be transmitted, so that amplifierssuch as these are relatively unsuitable for high-speed transmission suchas ADSL, since the dynamic losses rise in proportion to the switchingfrequency.

[0013] The already known amplifier circuits for line drivers aretherefore subject to the problem that none of these amplifier circuitsachieves high linearity and thus high efficiency in the signal to betransmitted with very low scatter at the same time.

[0014] Against the background of the prior art as described above, thepresent invention is thus based on the object of specifying a linedriver arrangement which produces a signal to be transmitted not onlywith high linearity and thus high efficiency but at the same time alsowith as little scatter as possible.

[0015] According to the invention, this object is achieved by anamplifier arrangement for a line driver having the features of PatentClaim 1.

[0016] According to Patent Claim 1, a line driver arrangement isprovided for driving signals via at least one subscriber line, having:

[0017] an input for injecting an input signal and having an output atwhich a signal which is to be driven via the subscriber line can betapped off,

[0018] a digital amplifier which produces a pulse-width-modulated signalon the output side from the input signal or from a signal derived fromit,

[0019] an analog amplifier, which produces an analog signal on theoutput side from the input signal or from a signal derived from it,

[0020] with the outputs of the amplifiers being coupled such that thesignal to be driven results from superimposition of the analog signaland the digital signal,

[0021] with the gain of the analog amplifier being matched to the gainof the digital amplifier such that scatter and/or overshoot on thedigital signal are at least reduced after the superimposition.

[0022] Advantageous refinements and improvements can be found in thedependent claims and in the description, with reference to the drawings.

[0023] The idea on which the present invention is based is to combinethe functionalities of a known Class D amplifier with those of a ClassAB amplifier such that both high linearity and high efficiency areachieved for the signal to be transmitted. The invention is thus basedon the knowledge that digital Class D amplifiers have very poorlinearity but very good efficiency. These digital amplifiers are used toproduce virtually all of the power for the signal to be transmitted onthe subscriber line, although the signal to be transmitted thus has poorlinearity. The analog Class A or AB amplifier, on the other hand, haspoor efficiency, but very good linearity. This analog amplifier is inthis case linked to the digital amplifier such that the severelydistorted signal from the digital amplifier is, so to speak, cleaned up.A signal to be transmitted with high linearity and high efficiency, thatis to say low scatter, is thus produced on the output side.

[0024] The functions of the two amplifiers are controlled by means of acontrol device.

[0025] This advantageous linking of the functionalities of the analogand digital amplifier is achieved, according to the invention, in atleast two different ways:

[0026] Firstly, the analog and digital amplifiers can be arranged inparallel with one another in the subscriber line. In this case, thesignals which are produced on the output side by the two amplifiers aresuperimposed on one another after being transformed in each case. Theamplified signal which is produced on the output side in this way istransmitted via the subscriber line. This has the particular advantagethat is actually this signal to be transmitted which is at the same timefed via a feedback loop with negative feedback into the input of theanalog amplifier. This feedback path, which is provided only in theanalog path of the driver circuit, is intended to compensate for thescatter that is inherent in the signal on the output side, as follows.Any scatter which may be present in the output signal and which reducesthe linearity on the output side is fed back via the feedback path, andis superimposed on the signal on the input side. The difference betweenthis signal and the fed-back signal thus represents a measure of thescatter. The negative feedback thus effectively results in a controlloop with negative feedback.

[0027] As an alternative to arranging the analog and digital amplifiersin parallel, these may also, for example, be arranged in series with oneanother, with the digital amplifier being downstream from the analogamplifier. The output signal from the analog amplifier is supplied onthe one hand directly and on the other hand via a resistance network andvia the digital amplifier to the output of the line driver. These twooutput signals are superimposed on one another and are transmitted viathe subscriber line, via a transformer. This output signal to betransmitted still does not have sufficient linearity, however. For thispurpose, the line driver circuit is equipped with negative feedback, inwhich the superimposed output signal from the two amplifiers has theinput signal of the analog amplifier superimposed on it via a feedbackpath with negative feedback. This overcomes the scatter in the outputsignal that is to overhang, by compensation for the waves and jaggedelements in the output signal from the digital amplifier.

[0028] The invention will be explained in more detail in the followingtext with reference to the exemplary embodiments which are illustratedin the drawing, in which, in this case:

[0029]FIG. 1 shows a block diagram of the general configuration of aline driver circuit according to the invention;

[0030]FIG. 2 shows the block diagram of a first line driver circuitaccording to the invention;

[0031]FIG. 3 shows a detailed circuit diagram for the line drivercircuit corresponding to that in FIG. 2;

[0032]FIG. 4 shows a block diagram of one refinement of the digitalamplifier as shown in FIGS. 2 and 3;

[0033]FIG. 5 shows the block diagram of a second line driver circuitaccording to the invention;

[0034]FIG. 6 uses a graph to show the time response of the outputcurrents which are produced by the amplifiers;

[0035]FIG. 7 shows a detailed circuit diagram of a line driver circuitcorresponding to that shown in FIG. 5; and

[0036]FIG. 8 shows the block diagram of a line driver as shown in FIGS.5 and 7.

[0037] Identical and functionally identical elements and signals areidentified in the same way—unless stated to the contrary—in all of thefigures of the drawing.

[0038]FIG. 1 uses a block diagram to show the basic principle of a linedriver according to the invention. The line driver is in this caseannotated by the reference symbol 1. The line carrier 1 has an input 2and an output 3, and is arranged in a subscriber line 4. The line driver1 has an analog amplifier 5 and a digital amplifier 6, whose outputsignals are linked to one another in a unit 7 which is providedspecifically for this purpose. A control unit 8 is also provided, inorder to control the two amplifiers 5, 6.

[0039] The digital amplifier 6 produces the power or the energy for datatransmission, the analog amplifier 5 improves the linearity and,depending on the implementation, a more or less complex control network8 is provided, in order to drive the two amplifiers 5, 6. Two of theseimplementations will be described in detail in the following text withFIGS. 2-8.

[0040]FIG. 2 shows the block diagram of a first line driver arrangementaccording to the invention. The line driver 1 in this case contains ananalog path 10 and a digital path 11, which are arranged in parallelwith one another between the input 2 and the output 3. The digital path11 has a digital amplifier 6, a filter 12 and a transformer 13, arrangedin series with one another. The analog path 10 has a matching circuit14, an analog amplifier 5 and a second transformer 15 arranged in serieswith one another.

[0041] The input signal Vi, which is injected via the input 2, is firstof all injected into the digital amplifier 6 in digital path 11, andthis digital amplifier 6 converts this signal to a pulse-width-modulatedsignal Vd, which can be tapped off on the output side of the digitalamplifier 6. The digital amplifier 6 thus produces the power which isrequired for data transmission. This PWM signal Vd is then filtered inthe filter 12, which is typically a low-pass filter, and is supplied tothe primary side of the first transformer 13. The transformer 13 usesthe digital, filtered PWM signal Vd′ to produce an analog signal Vowhich can be tapped off on the secondary side of the transformer 13.This analog signal in the ideal case forms the output signal Vo which isto be transmitted via the subscriber line 4.

[0042] Furthermore, the input potential Vi is first of all supplied tothe matching circuit 14 in the analog path 10. The potential Vi which isproduced on the output side of the matching circuit 14 is supplied tothe input Ve′ of the analog amplifier 10. The output signal from theanalog amplifier 5 is transformed via a second transformer 15, and issupplied to the output 3 of the line driver 1. The unit 7 for linkingthe output signals from the analog path 10 and from the digital path 11is provided there for this purpose, so that the signal Ve′ which isproduced from the analog path 10 has the output signal Vd′ from thedigital path 11 superimposed on it, with a negative mathematical sign.The result of this superimposition forms the analog output potential Vo.

[0043] In addition, a feedback path 16 is provided. The output signal Vocan be fed back with negative feedback to the input of the analogamplifier 5 via this feedback path 16. The feedback path 16 has adivider 18 with a feedback factor f. The analog output signal Vo is thusconverted via this feedback factor f to a signal Vo′ which is derivedfrom it and has the input signal Ve′ superimposed on it, with a negativemathematical sign, in the unit 17. The signal Vi which is obtained fromthis superimposition is injected into the input side of the analogamplifier 5. This results in a control loop with negative feedback.

[0044] The matching circuit 14 is used for the purpose of matching thephase and amplitude of the signal Vo′ which is fed back via the feedbackpath 16, on the input signal Vi′. Without this matching circuit 14, theanalog amplifier 10 would be overloaded. This matching is requiredbecause only a signal which is derived from the output signal Vo andwhich has only the scatter in the output signal Vo, but not any otherscatter, is intended to be provided as the feedback signal Vo′. If nosuch matching circuit 14 were provided, then the control loop forregulating out any scatter in the output signal Vo will be very muchless effective, and this would lead to reduced linearity in the outputsignal Vo.

[0045] In one basic implementation, the matching circuit 14 could be inthe form of a simple low-pass filter. In addition, a functional unit fortrimming may also be implemented, in order to improve the accuracy ofthis matching process.

[0046] The method of operation of the line driver arrangement 1according to the invention will be described in more detail in thefollowing text with reference to FIG. 2:

[0047] The high scatter in the digital path 11, which is caused by thedigital amplifier 6, results in an output signal Vout which hasundesirable scatter. The output voltage Vout of the output 3 is thus:

Vout=Vo+THD,   (1)

[0048] where THD denotes the harmonics that are superimposed on thesimple signal. This output signal Vout is at the same time compared withthe input signal Vi′ via the feedback path 16, in which it is divided bythe feedback factor f. As a result of this comparison, the comparator 17produces an error signal Ve, which is injected into the analog amplifier5. In the ideal case, in which there is no delay in the digital path 11and no matching is provided or required in the circuit 14, then Vi′=Vi.The error signal Ve thus becomes: $\begin{matrix}{{Ve} = {{{Vi} - \frac{Vout}{f}} = {{{Vi} - \frac{{Vo} + {THD}}{f}} = {{Vi} - \frac{Vo}{f} - \frac{THD}{f}}}}} & (2)\end{matrix}$

[0049] If the error factor f is chosen as follows: $\begin{matrix}{f = \frac{Vo}{{Vi}^{\prime}}} & (3)\end{matrix}$

[0050] then the error signal Ve becomes: $\begin{matrix}{{Ve} = {- \frac{THD}{f}}} & (4)\end{matrix}$

[0051] For the situation where the analog amplifier 5 is an invertingamplifier which has very high gain in the region of the feedback factorf, then a transformation ratio in the transformer 15 of 1:1 for theoutput signal Ve′ results in:

Ve′=−THD   (5)

[0052] If the output signals Vout, Ve′ from the digital path 11 and theanalog path 10 are superimposed, this results in the ideal case, on thebasis of the assumptions made above, in the scatter in the output signalbeing corrected completely.

[0053] However, in reality, there is always a certain time delay in thedigital path 11, so that a constellation according to equation (3) is inpractice not feasible. For these reasons, a matching circuit 14 isadvantageously provided, which uses the input signal Vi to produce anoutput signal Vi′ such that the equation (3) is very largely satisfied.At the same time, this means that the phase and magnitude of the outputsignals Vo and Ve′ are optimally matched to one another. However, thisis never entirely possible in reality, and in fact there is always stilla certain mismatch. According to equation (2), a mismatch such as thiswould add to the original scatter. However, this would result in theproblem that the analog amplifier 5 would interpret this mismatch asscatter caused in the digital amplifier 6, and would thus attempt tocorrect it in the output signal Vout. The error signal Ve thus becomes:$\begin{matrix}{{Ve} = {{mism}.{- \frac{THD}{f}}}} & (6)\end{matrix}$

[0054] so that, even in the ideal case in which the scatter has beencorrected completely, the mismatch in the output signal Vout is evidentas follows:

Vout=Vo+mism.*f   (7)

[0055] For these reasons, it is very important for an output signal Voutwhich is very largely free of scatter and thus of the best possiblelinearity, to match the two signals in the analog and digital paths 10,11 as well as possible.

[0056]FIG. 3 shows a more detailed exemplary embodiment for theimplementation of a line driver 1 as shown in FIG. 2. In the example inFIG. 3, it is assumed that the line driver 1 is designed to amplify anADSL signal via the subscriber line 4. The subscriber line which, forexample, is a typical two-wire telephone line, has, for example, animpedance of 100 Ohms, with the normal tolerances on this. The maximumamplitude of the ADSL signal would therefore be about 18 V. The signalto be transmitted is a multitone signal comprising 256 individual tonesin the frequency band between 138 kHz and 1.1 MHz, with a frequencyseparation between adjacent tones of about 4 kHz, which is obtained fromthe quadrature amplitude modulation (QAM). The crest factor whichresults from this is then up to 6.

[0057] The line driver 1 as shown in FIG. 3, which is in the form of abuffer amplifier, has an additional preamplifier 20, whose input side isconnected to the inputs 2 and whose output side is arranged upstream ofthe digital path 11 and analog path 10. Pesistors 21 are connectedupstream of the differential inputs of the preamplifier 20. Furthermore,resistors 22 are provided to bridge the inputs and outputs of thepreamplifier 20.

[0058] In the digital path 11, the preamplifier 20 is followed by thedigital amplifier 6 and the filter 12.

[0059]FIG. 4 uses a block diagram to show the refinement in a digitalamplifier 6 as shown in FIG. 3. The digital amplifier 6 has a comparator30, which is coupled to the inputs of the amplifier 6 and is clocked viaan externally produced clock CLK, for example at 7.8 MHz. Thedifferential outputs of the comparator 30 are respectively followed bytwo output stages 31, 32, which are driven via a respective gate controlcircuit 33, 34. The two output stages 31, 32 are each arranged withtheir load circuit between a first and a second supply potential Vdd,GND.

[0060] The output stages 31, 32 are in this case in the form of powerinverters, in order to switch the high current which is required in theload 26. The power inverters 31, 32 thus produce a pulse-width modulatedsignal Vd at their output.

[0061] In the analog path 10 in FIG. 3, the outputs of the preamplifier20 are first of all connected to the matching circuit 14 and, via theseries resistors 23, to the differential inputs of the analog amplifier5. The resistors 23 have a resistance R1. The differential outputs ofthe analog amplifier 5 are coupled to the outputs 3 via the transformer13. In this case, the transformer 12 once again has a transformationratio of 1:6. Furthermore, the resistors 24 with a resistance R2 arearranged between the outputs of the transformer 13 and the inputs of theanalog amplifier 5.

[0062] The resistor 24 is a component of the feedback path 16, so thatthe feedback factor is given by: $\begin{matrix}{f = \frac{R2}{R1}} & (8)\end{matrix}$

[0063] A further resistor 25, whose resistance is Rm is provided in theoutput path of the line driver 1, that is to say in the lines which areprovided between the transformer 13 and the output 3. At its output 3,the line driver 1 has a load 26 whose impedance is RL.

[0064] The line driver circuit 1 also has a feedback path 28, which tapsoff the output voltage Vo of the output 3 of the line driver 1 andinjects it with positive feedback via resistors 27 into the differentialinputs of the preamplifier 20. This thus results in a control loop withpositive feedback.

[0065] The output resistor 25, the load 26 and the feedback path 28 thusresult in a network for a synthesized impedance, with the synthesisfactor m of this synthesized impedance being obtained as follows:$\begin{matrix}{m = \frac{R_{LOAD}}{2{Rm}}} & (9)\end{matrix}$

[0066] The positive feedback of the output voltage in this case makes itpossible to reduce the voltage drop across the output transistor.

[0067] The line driver 1 shown in FIG. 3 is completely differential,that is to say the analog and digital amplifiers 5, 6 as well as thepreamplifier 20 each have two differential inputs and two differentialoutputs. The preamplifier 20 and the analog amplifier 5 are in the formof inverting amplifiers.

[0068] The block diagram in FIG. 5 shows a second line driverarrangement according to the invention. In this case, the line driver 1has an analog amplifier 5, into which the input signal Vi is injected.The analog amplifier 5 is connected on the output side via a resistancenetwork 40 to the primary side of the transformer 13. The resistancenetwork 40 thus uses the output signal Vo′ from the analog amplifier 5to produce a current signal i_(a). Furthermore, a digital amplifier 6 isprovided between the resistance network 40 and the primary side of thetransformer 13. A voltage signal Vs which is tapped off from theresistance network 40 is injected into the digital amplifier 6. On theoutput side, the digital amplifier 6 produces a current signal i_(d),which, as a result of superimposition with the current signal i_(a),leads to the output current signal i_(o). This is supplied to theprimary side of the transformer 13, which uses this to produce thesignal V_(line) to be transmitted, on its secondary side.

[0069] In addition, a feedback path 41 is provided, via which the outputcurrent signal i_(o) or the voltage signal Vo derived from it, is fedback with a negative mathematical sign. The output voltage signal Vobecomes the feedback signal Vf in the feedback path 41, on which theinput signal Vi is superimposed. This results in the error signal Ve,which is injected into the analog amplifier 5.

[0070] Thus, in this case, the analog amplifier 5 acts as a bufferamplifier in order to control the digital amplifier 6.

[0071] The method of operation of this circuit will be explained brieflyin the following text with reference to FIG. 5:

[0072] Since the digital amplifier 6 has a pulse-width modulatorcharacteristic, its output current id changes its mathematical signcyclically. This means that i_(o) and Vo are also reversed, as a resultof which the analog current i_(a) is also forced—via the closed circuitrepresented by dashed lines in FIG. 5—to change its mathematical sign,so that the mathematical sign of V_(s) also changes. However, inconsequence, the digital amplifier 6 switches once again, thus closingthe circuit.

[0073] The self-oscillation is produced in the inner control loop of thedigital amplifier 6. This inner control loop is shown by dashed lines inFIG. 5. The current id is generated by the measurement voltage V_(s).When the digital current id reverses, then the current i_(o) alsoreverses, as a result of which the current i_(a) changes itsmathematical sign. V_(s) thus also changes its mathematical sign, thusresulting in the control loop.

[0074] This is a self-oscillating control loop, so that in this casethere is no need for any external clock for the digital amplifier 6.

[0075] The feedback delay in this control loop thus limits the switchingfrequency of the self-oscillating control loop. However, as before, thisresults in inadequate linearity.

[0076] In order to optimize the linearity, the line driver 1advantageously has the additional feedback path 41. This feedback path41 is used to inject an error signal Ve from the output current signali_(o) into the analog amplifier 5. The error signal is thus:

Ve=Vi−Vf=Vi−Vo·f   (10)

[0077] where f denotes the feedback factor. The feedback reduces theerror signal Ve, thus very largely correcting any scatter in the outputsignal i_(o). This is achieved by means of the analog current signali_(a), in which any ripple which is superimposed on the digital currentsignal i_(d) is compensated for.

[0078] The output current signal i_(o) is obtained, as is shown in FIG.5, as follows:

i _(o) =i _(a) +i _(d) =i _(a)+(k+i _(a))=(1+k)i _(a),   (11)

[0079] with the digital current i_(d) being a multiple k of the analogcurrent i_(a), by means of the digital amplifier 6. In the situationwhere k is very large, then:

i _(o) ≈k·i _(a) =i _(d)

[0080] At the same time, this means that the output current i_(o)corresponds essentially to the current i_(d) which is produced by thedigital amplifier 6 and which has very high efficiency. It also followsfrom the block diagram in FIG. 5 that:

i _(d) =g _(d)·Vs,   (13)

Vs=A _(R)·i_(a),   (14)

[0081] with the gain factor k of the digital amplifier 6 being obtainedas follows:

k=g _(d) ·A _(R)   (15)

[0082] In order now to increase the efficiency of the line driveraccording to the invention as shown in FIG. 5, all that is necessary istherefore to increase the current i_(d) in the digital amplifier 6 withrespect to the analog current i_(a) in the analog amplifier 5.

[0083]FIG. 6 shows a current/time graph, determined by simulation, for aline driver arrangement 1 shown in FIG. 5. Superimposition of the analogcurrent signal i_(a) and the digital current signal i_(d) results in theoutput current signal i_(o), which now has virtually no harmonics.

[0084]FIG. 7 shows a detailed circuit diagram of a line driver accordingto the invention as shown in FIG. 5. In this case, the line driver 1 isonce again completely differential.

[0085] The analog amplifier 5, which is once again in the form of aninverting amplifier, is connected via the input resistors 42 to theinput 2. The differential outputs of the analog amplifier 5 are coupledvia the resistance network 40 to the primary side of the transformer 13.The resistance network 40 has taps 43, via which a voltage signal Vs canbe injected into the inputs of the digital amplifier 6. The differentialoutputs of the digital amplifier 6 are coupled via resistors 7 to theprimary side of the transformer 13.

[0086]FIG. 8 uses a block diagram to show the configuration of a digitalamplifier 6 corresponding to that shown in FIG. 7. In this case, thedigital amplifier 6 has a comparator 50, whose inputs are connected tothe differential inputs of the digital amplifier 6. The two outputs ofthe comparator 50 are connected to a respective output stage 51, 52. Theoutput stages 51, 52 in this case have gate control circuits 53, 54 fordriving them and for driving the respective transistors in the outputstages 51, 52 connected upstream of them. These output stages 51, 52 arein the form of power inverters. An output signal Vd can be tapped off atthe center taps of the respective output stages 51, 52 and can besupplied via the inductances 55, 56 to the differential outputs of thedigital amplifier 6. The inductances 55, 56 use the voltage signals Vdwhich can be tapped off at the center taps of the output stages 51, 52to produce a current signal i_(d), in each case. Furthermore, theseinductances 55, 56 act, so to speak, as filters, with their inductancevalue being very important for the stability of and for compensation ofthe output current.

[0087] The resistance network 40 comprises two measurement resistances44, which are arranged in parallel with one another with respect to thedifferential outputs of the analog amplifier 5 and are coupled on bothsides via the resistances 45 to one another, crossed over. Two of theseresistances 45, which are coupled and crossed over, in each case form avoltage divider in this case, that is center taps 43 the input potentialVs for the digital amplifier 6 is tapped off. The outputs of theresistance network 40 are, as already mentioned, coupled on the one handto the primary side of the transformer 13 and on the other hand via aresistor 46 to the inputs of the analog amplifier 5. The resistors 46 inthis case once again define a feedback for the analog amplifier 5.

[0088] The output voltage from the analog amplifier 5 is thus measuredvia the measurement resistor 44, and is thus used to drive the digitalamplifier 6. This highly advantageous arrangement means that there is noneed to further amplify the output voltage signal from the analogamplifier 5 for injection into the digital amplifier 6. All that isnecessary is to be sure that the measurement resistance 44 is chosen tobe as small as possible, in order to keep the voltage drop, and hencelosses across the measurement resistance 44 as small as possible. Theresistances 45 in the voltage divider should in contrast be designed tobe very much greater than the measurement resistance 44, so that theycarry only a comparatively small current.

[0089] The voltage Vo which is dropped across the primary side of thetransformer 13 is transformed to the secondary side with atransformation ratio of 1:8 in the present exemplary embodiment, so thatthe signal V_(line) to be transmitted can be tapped off at the output 3of the line driver.

[0090] A further very important relationship results from the switchingfrequency. The switching frequency f_(sw) for a line driver circuit 1 asshown in FIG. 7 is as follows: $\begin{matrix}{f_{SW} \propto \frac{1}{L \cdot V_{{T \cdot \Delta}\quad t^{\prime}}}} & (16)\end{matrix}$

[0091] where L is the value of the inductances 55, 56, V_(T) is thethreshold voltage of the comparator 50 for the digital amplifier 6, andΔt is the delay in the control loop.

[0092] However, equation (16) applies only to an inductance value in arange in which it is possible to sufficiently well model the current inthe digital amplifier 6. However, as already mentioned above, the delayΔt in the digital control loop limits, so to speak, the switchingfrequency f_(SW). For this situation, the switching frequency f_(SW) isdetermined using the following equation: $\begin{matrix}{{f_{SW} \propto \frac{{i_{d}(t)}}{t}} = \frac{V_{DD} - {V_{D}(t)}}{L}} & (17)\end{matrix}$

[0093] where V_(DD) denotes the supply voltage for the digital amplifier6, and V_(D)(t) denotes the output signal for the digital amplifier 6.

[0094] Equation (17) thus indicates the frequency range in which theentire line driver arrangement 1 operates correctly, that is to say theswitching frequency f_(SW) is directly proportional to the rate ofchange of the digital current i_(d), and is thus inversely proportionalto the signal amplitude. This knowledge can be used to find the optimumswitching frequency for the line driver 1. Furthermore, equation (17)allows the power consumption of the line driver arrangement 1 to beoptimally matched to the given conditions.

[0095] The present invention has been described above on the basis of aline driver for an ADSL data transmission device. However, the inventionis not restricted exclusively to ADSL systems, but can be used highlyadvantageously with line drivers for any desired xDSL systems.Furthermore, the invention is also not restricted to specific linedriver types and classes, but, within the scope of the invention, may,of course, be used for any desired line drivers in which the requirementfor great linearity with scatter and losses which are as low as possibleat the same time is a primary factor.

[0096] Thus, in summary, it can be stated that the arrangement accordingto the invention makes it possible to provide a line driver in a highlyelegant but very effective manner, with both low scatter and highefficiency.

[0097] The present invention has been illustrated on the basis of theabove description in such a way as to explain the principle of themethod according to the invention and its practical application as wellas possible, although the invention may also, of course, be produced inmany different variants, if suitably modified.

1. A line driver for driving signals via at least one subscriber line,comprising: an input for injecting an input signal and an output atwhich a signal which is to be driven via the subscriber line is tappedoff, a digital amplifier which produces a digital signal on the outputside from one of the input signal or a signal derived from the inputsignal, an analog amplifier, which produces an analog signal on theoutput side from one of the input signal or a signal derived from theinput signal, wherein the outputs of the amplifiers are coupled suchthat the signal to be driven results from superimposition of the analogsignal and the digital signal, and wherein the gain of the analogamplifier is matched to the gain of the digital amplifier such that atleast one of the scatter or overshoot on the digital signal is at leastreduced after the superimposition.
 2. The line driver of claim 1, andfurther comprising a feedback path via which the signal which resultsfrom the superimposition of the analog and digital signals is fed backwith negative feedback to the input of the analog amplifier.
 3. The linedriver of claim 2, wherein the analog amplifier is arranged in an analogpath, and the digital amplifier is arranged in a digital path, with thetwo paths being arranged in parallel with one another.
 4. The linedriver of claim 3, and further comprising a filter following the digitalamplifier in the digital path and carrying out frequency smoothing aswell as filtering of the digital signal.
 5. The line driver of claim 3,and further comprising a matching circuit connected upstream of theanalog amplifier in the analog path and carrying out at least one ofphase matching or amplitude matching of the input signal to the outputsignal.
 6. The line driver of claim 3, wherein the analog amplifier isfollowed by a resistance network, at whose output an analog current istapped off, and wherein a potential which is tapped off from theresistance network is injected into the digital amplifier to produce onthe output side a digital current which is superimposed on the analogcurrent.
 7. The line driver of claim 6, wherein the resistance networkhas at least one measurement resistance via which the analog current ispassed, and has a voltage divider across which the potential which isinjected into the digital amplifier is tapped off.
 8. The line driver ofclaim 7, wherein the resistance value of the measurement resistance isvery much less than the resistance values of the voltage dividerresistances.
 9. The line driver of claim 3, and further comprising atleast one transformer is provided at the output of the line driver. 10.The line driver of claim 2, and further comprising a load which is inthe form of a transformer provided at the output of the line driver. 11.The line driver of claim 9, wherein the transformer is designed suchthat its bandwidth matches the bandwidth of the signal to be driven. 12.The line driver of claim 9, wherein at least one transformer has a veryhigh transformation ratio in the region of at least 1:4 between theprimary and the secondary sides.
 13. The line driver of claim 11 andfurther comprising a further transformer arranged in the analog pathfollowing the analog amplifier.
 14. The line driver of claim 13, whereinthe further transformer has a lower transformation ratio than the firsttransformer.
 15. The line driver of claim 14, and further comprising adivider provided in the feedback path having a feedback factor by whichthe fed-back signal is divided.
 16. The line driver of claim 15, whereinthe feedback factor (f) corresponds to the transformation ratio of thetransformer which follows the digital amplifier.
 17. The line driver ofclaim 10, further comprising a further feedback device which feeds backthe output signal with positive feedback to the input, with the elementsof the control loop which results from this being designed such that theimpedance of the line driver is variable.
 18. The line driver of claim17, wherein the variable impedance has a synthesis factor (m) which isproportional to the ratio of the load to an output resistance (25). 19.The line driver of claim 3, and further comprising a control devicecontrolling the amplifiers.
 20. The line driver of claim 3, wherein theanalog amplifier is in the form of an inverting amplifier.
 21. The linedriver of claim 19, wherein the digital amplifier has a comparatorcoupled to the input of the digital amplifier followed, as the outputstage, by a power inverter.
 22. The line driver of claim 3, wherein thedigital amplifier has a PWM characteristic, such that its digital outputsignals are pulse-width modulated.
 23. The line driver of claim 3,wherein the line driver is in the form of an ADSL driver circuit. 24.The line driver of claim 22, wherein circuit means are provided, bymeans of which the switching frequency is matched to the amplitude ofthe output signal.
 25. The line driver of claim 3, wherein the signalsto be driven are speech signals or data signals.
 26. The line driver ofclaim 3, wherein the line driver is completely differential.
 27. Theline driver of claim 9, wherein at least one transformer has a very hightransformation ratio in the region of more than 1:6, between the primaryand the secondary sides.
 28. The line driver of claim 13, wherein thefurther transformer has a transformation ratio of about 1:1.
 29. A linedriver for driving signals via a subscriber line, comprising: an inputfor injecting an input signal; an output at which a signal which is tobe driven via the subscriber line is tapped off; a digital path betweenthe input and output including a digital amplifier which produces apulse-width-modulated (PWM) signal on an output side of the digital pathfrom a signal derived from the input signal; an analog path between theinput and output including an analog amplifier which produces an analogsignal on an output side of the analog path from a signal derived fromthe input signal; wherein the digital path and analog paths are arrangedin parallel with one another and are coupled at their output sides suchthat the signal to be driven results from superimposition of the analogsignal and the PWM signal; and wherein the gain of the analog amplifieris matched to the gain of the digital amplifier such that at least oneof the scatter or overshoot on the PWM signal is at least reduced afterthe superimposition.
 30. The apparatus of claim 29 and furthercomprising a feedback path via which the signal which results from thesuperimposition of the analog and PWM signals is fed back with negativefeedback to an input of the analog path.